IWIPP Programme Booklet

For presentation abstracts please see below the booklet, for Keynote Abstracts please go to http://iwipp.org/keynotes/


Wednesday 24th August

0830 – 0845: Welcome Comments – Francesco Iannuzzo, Aalborg University

0845 – 0935: Keynote 1 – Eckart Hoene, Fraunhofer (http://iwipp.org/keynotes/)

0935 – 1025: Power Modules 1


0935 – 1000: “Design of a Test Package for High Voltage SiC Diodes” Arthur Boutry, SuperGrid Institute, France

A custom package for SiC diodes is presented. It is designed to accommodate ”research-grade” devices (available in small quantities, with large variations in characteristics, and, in our case, poor topside metallisation). It allows testing of the diodes at high voltage (> 5kV) and high current (600 A). The packaged diodes described here are used as a drop-in replacement for Si diode modules in a double-pulse setup. The packaging design is based on a ”sub-package” approach, to achieve high production yield and facilitate exchange of devices failing during the tests. Packaging technologies include silver sintering for the die attach and the use of an original die topside pressing system with spring probes. Experiments validate the concept of the package.


1000 – 1025: “Protecting Power Semiconductors from H2S Gases” Björn Rentemeister, Infineon, Germany

The market penetration of variable-frequency drives (VFD) has been growing consistently over the years. Nowadays, VFDs are widely used in many industrial applications. In some applications, such as paper production, mining, and the rubber industry, it is plausible that power semiconductors are impacted by corrosive gases. Corrosion, in general, is caused by a chemical reaction between a metal and external substances, and occurs at the interface of the metal and the environment. For electronic components, acidic gases are the most harmful corrosive substance. Their impact may worsen if there are fluctuations in temperature or humidity. It can lead to condensation and formation of conductive solutions on and within the electronic components.This presentation discusses the: relevant standards,  impact of H2S on the corrosion of Cu electrodes under applied bias and its effect on power electronics operating in the field, correlation between field experiences and the development of an accelerated H2S test, the impact of H2S on standard and protected modules under specific test conditions.


1025 – 1045: Coffee Break

1045 – 1200: Power Modules 2


1045 – 1110: “Harmful Gas Requirements for Power Electronics” Victoria Zimmerman, Fraunhofer, Germany

Chemically active substances significantly impact the reliability of semiconductor devices. Corrosion and other lifetime relevant effects can be accelerated by presence of critical chemical substances like hydrogen sulfide (H2S), sulfur dioxide (SO2), nitric oxides (NOx) and chlorine (Cl2). Comprehensive knowledge of their concentration in the environment and combination with other acceleration parameters is required to design and qualify semiconductor devices and converters with the required robustness. For power electronic systems in “normal” industrial environments, i.e. without specifically enhanced chemical exposure, system designers often target IEC 60721-3-3 Class C2 conditions, describing urban regions with industrial activity and heavy traffic. Aim of this work was to improve the database for concentration profiles of the hazardous gaseous contaminants and to relate the data with the standard. Comprehensive research into the contaminants of interest over Europe shows that a lot of data are publicly available for SO2 and NO2/NO3. Data for H2S and Cl2, however, had to be collected by a field measurement campaign using dedicated sensor systems. Typical concentrations are significantly below the values given by the standards for H2S but even more for Cl2, SO2 and NOx. Thus, the use of the standard should be observed critically.


1110 – 1135: “Modular and Double-Sided Air-Cooled Power Module with Paralleled Switching Cells” Yvan Avenas, G2Elab, France

The TAPIR technology (compacT and modulAr Power modules with IntegRated cooling) is based on the modular assembly of air-cooled switching cells. It requires a multiphysics analysis to prove its interest compared to current power module solutions. To contribute to this objective, this presentation focuses on magnetic aspects and, more specifically, on stray inductance evaluation. An experimental method for evaluating stray inductance and magnetic coupling between cells is proposed and the results are compared with simulations. Then, magnetic simulations are carried out to evaluate the stray inductance of nearby paralleled switching cells. Thanks to this analysis, an assembly with alternated switching cells is proposed to decrease the global stray inductance of the power module.


1135 – 1200: “Modeling Approach for Design Selection and Reliability Analysis of SiC Power Modules” Ivana Kovacevic-Badstuebner, ETH Zurich, Switzerland

This paper presents a 3D electro-thermo-mechanical modeling approach developed for analysis of reliability aspects of different Silicon Carbide power MOSFET packages. The proposed approach includes a new distributed model of conduction losses within a power MOSFET die, and hence, enables more accurate electro-thermal simulations of parallel SiC power MOSFETs. In a consecutive thermo-mechanical simulation step, the plastic damage indicators are extracted from the calculated stress-strain fields within the package. This allows a comparative study between different packaging technologies in terms of wear-out failures. Furthermore, the proposed modeling platform can provide a deeper insight into failure modes of SiC power MOSFET packages during accelerated power cycling testing. The modeling approach is presented on an example of a 3D layout of a multi-chip power module.


1200 – 1300: Lunch

1300 – 1350: Keynote 2 – Tamara Baksht, VisIC (http://iwipp.org/keynotes/)

1350 – 1440: Manufacturing Processes 1


1350 – 1415: “Insights into the Layouts of Power Semiconductor Chips” Peter Friedrichs, Infineon, Germany



1415 – 1440: “Non-CMOS Compatible SiC Power Device Fabrication in Volume Si Fabs” Victor Veliadis, NCSU, USA

SiC devices are displacing their incumbent Si counterparts in several high volume power applications. As SiC market share continues to grow, the industry is lifting the last barriers to mass commercialization that include higher than Si device cost, relative lack of wafer planarity, the presence of basal plane dislocations, reliability and ruggedness concerns, and the need for a workforce skilled in SiC power technology to keep up with the rising demand. To enable cost effective SiC manufacturing, high yielding fabrication processes are required. Numerous well-established silicon technology processes have been successfully transferred to SiC. However, SiC material properties necessitate development and optimization of specific processes including wafer thinning, etching, heated implantation and anneal, and low resistivity Ohmic contact formation. In this presentation, we will review key aspects of SiC fabrication technology and outline non-CMOS compatible processes that have been streamlined to allow for mass SiC device fabrication in standard Si fabs. The presentation will conclude with a brief introduction of the 75-member PowerAmerica consortium, which spans all aspects of the WBG supply chain, its US$146M investment in 200 applied WBG projects, and its education and workforce development efforts that trained 410 full-time students and engaged over 4100 attendees in WBG related learning activities.


1440 – 1500: Coffee Break

1500 – 1615: Manufacturing Processes 2


1500 – 1525: “Thermomechanical Analysis of Si-Chip Fracture Caused by Double-Sided Ag Sintering for PCB Packages” Ankit Bhushan Sharma, Hochschule Kempten, Germany [Virtual]

Previously, a novel concept for PCB embedding of power semiconductors with reinforced top contacts has been published by our group. In this work, a thermomechanical study is performed to understand the fracture probability of the chip during fabrication. The ballon-ring (BOR) and ball-on-edge (BOE) tests are employed to characterize the chip strength. A probabilistic model is used to evaluate the failure probability. The contribution of different fabrication steps to the overall failure probability is investigated. A parametric analysis is performed to analyze the impact of material choice and the thickness of the substrate and the interposer. A single-step sintered package with a 200 µm thick Cu interposer and an 800 µm thick Cu substrate with hard Cu leads to a 12% failure probability compared to 52% for an identical stack with a soft Cu substrate. The top surface failure probability for a 150 µm thick CIC interposer is 0.016% compared to 8.6% for a 100 µm Cu interposer, for an identical 800µm thick Cu substrate. A sinterlamination process, where the die-attach and curing of the prepreg material simultaneously take place, results in a 0.03% failure probability.


1525 – 1550: “Process Advantages of Thermosonic Wedge Bonding Using Dosed Tool Heating” Michael McKeown, Hesse Mechatronics, USA

Thermosonic wedge bonding has a number of advantages over room-temperature ultrasonic wire bonding. However, it is rarely used besides ball bonding and gold wedge applications due to the drawbacks and limitations of available heating technologies. Hesse recently introduced a novel thermosonic process using a laser-heated bonding tool which will alleviate most of the drawbacks. This paper presents the results of bonding tests that have used this novel process to bond aluminum and copper heavy wire to sheets of the same metal. The opportunity for fine gold wedge bonding using this novel approach will also be reviewed.


1550 – 1615: “Usage of NanoWires in Power Modules and Frequency Converters” Olav Birlem, NanoWired GmbH, Germany

Bare dies like IGBTs, MOSFETs and Diodes on a DCB-substrates have a wide range of applications like frequency converters or inverters in renewable energy plants or sustainable transport like electric vehicles. The lifetime and the power density of such devices are strongly influenced by the used die attach materials. Conventional lead-free eutectic or near eutectic soldering processes are suitable for mounting bare dies on a DCB, but they suffer from high temperatures and poor reliability due to the formation of intermetallic layers (IMC). Thus, more and more companies are introducing a silver-sintering process. Silver sintering requires lower temperatures than soldering, and enables a high temperature operation of the device. Nevertheless, silver sintering has some drawbacks, like a higher process effort (printing, drying, die attach and sintering), a CTE mismatch, and last not least the high material cost of silver. One solution for these issues is, to use copper nanowires for sintering. NanoWired has developed three possibilities to integrate metallic nanowires into the sintering process.


1615 – 1745: Welcome Reception (Combined with Poster Session)

1615 – 1745: Poster Session


1615 – 1745: “Cu-Sintering for Highly Reliable Interconnects” Hans-Jürgen Albrecht, budatec GmbH, Germany 

There is an increasing demand for high-power electronic systems from various industrial sectors including e.g. automotive, power infrastructure and aerospace. The sinter-bonding reactions and mechanical strength of Cu-sintered joints with Ag-surface finished SiC chip and DBC and organic substrates were evaluated during the sintering process. These Cu interconnets are required to function faster, operate more efficiently, and most importantly, withstand extreme conditions and high temperature without having reliability issues. Therefore, there remains a need for alternative, environmental-friendly, cost-effective die-attach materials for packages that operate at high temperature conditions.


1615 – 1745: “Investigation of Space Charge Accumulation Formed in an Insulating Later of Motor Windings by Voltage Application Through Air Gap” Shunya Tanaka, Tokyo City University, Germany 

The accumulation of space charge in insulating material and its effect on the discharge inception voltage are investigated by measuring the space charge distribution formed in it by applying a dc voltage to it through the air gap. In the previous study, the accumulation of space charge in the material was observed by applying the dc voltage to it through contacted electrodes. However, in an actual usage, the voltage is applied to the material through the air gap. Therefore, we attempted to conduct the measurement of the space charge distribution in a sample with an air gap. As a result, it was found that the space charge accumulation enhanced a discharge.


1615 – 1745: “Liquid Metal in Power Electronics” Nick Baker, University of Alabama, USA 

The presentation will focus on the use of liquid Gallium as the front-side interconnection for semiconductor chips. Results from a 200A diode and a 70A IGBT will be presented. Compared to Aluminium wire-bonds, the liquid Gallium based front-side interconnect increased chip lifetime by a factor of between 5x-10x.


1615 – 1745: “Hybrid Variable Frequency Drive with Active Magnetic Bearing for Space Application” Bela Kagalwala, Calnetix, USA 

This paper describes hardware design considerations and performance results of a new state of the art fully integrated hybrid (dual) controller developed for driving a fractional horsepower compressor motor on magnetic bearings for space applications. To improve performance and reliability of compressor motor, magnetic levitation (magnetic bearings) has been used in lieu of more conventional bearings (e.g., ball bearings or air bearings). This improves resistance to contaminants and enable extensibility with regards to blower speed, pressure rise and mass flow rate. The hybrid integrated controller consists of a high-performance Variable Frequency Drive (VFD) and Magnetic Bearing Controller (MBC).


1615 – 1745: “Double Side Cooled Package Based on SiC Trench MOSFETs Enables High Performance for Automotive Drive Train Applications” Ajay Poonjal Pai, Infineon, Germany 

This paper presents a high performance Double Side Cooled (DSC) module based on trench Silicon Carbide (SiC) MOSFETs, and demonstrates the design of an optimized cooler. The cooler’s thermal performance is simulated and experimentally verified. The static and switching characteristics of the SiC module are experimentally characterized and compared against a Silicon- (Si) based DSC Module to determine the benefits of SiC at the module and inverter levels.


1615 – 1745: “An LTSpice – MATLAB Interface for Mitigating Convergence Problems in Circuit Optimization with SPICE” Pawel Kubulus, Aalborg University, Denmark 

With the recent emergence of wide-bandgap semiconductors the power electronics design process moves gradually towards the digital space. However, SPICE software that is a dominant tool for accurate transient analysis still lacks in both functionality and robustness needed in order to explore large design spaces unveiled by the digital twin models. In this work, a SPICE circuit solver has been interfaced with MATLAB programming environment. Compared to the literature, main focus has been put on mitigating convergence errors inherent to SPICE solvers without altering the solver algorithm itself. Convergence becomes a crucial problem when SPICE is used for optimization within a big solution space, therefore it is necessary to ensure it. This was achieved by implementing parameter variation based on circuit element tolerance, solver parameter adaptation and initial condition inheritance. The effects of each approach are compared for the case of Double-Pulse Test circuit, by the means of Not-a-Number (NaN) results proportion and runtime.


1615 – 1745: “Digital Design of 10kV SiC-MOSFET Power Module to Improve Wire-Bonding Layout for Power Cycle Capabilities” Masaki Takahashi, Aalborg University, Denmark 

Determining the reliability of 10 kV SiC-MOSFET power modules experimentally, is challenging due to the low number of samples available in the market. A digital design based on 3D thermal calculations is demonstrated to improve reliability capability in a 10 kV SiC-MOSFET power module. The module design was determined based on the calculation with digital twin modelling. The correctness of the digital twin model was confirmed by fabricating a 10kV SiC-MOSFETs power module sample and comparing the calculation temperature with the measured results. The design was focused on aluminum wires on chips, and the effect of the wire temperature by changing the wire layout was clarified. The results show that the improved wire layout reduces the wire temperature by 2.2-5.3% compared to the conventional design. This is expected to increase the power cycle capability by up to 31%, according to predictions based on the Coffin-Manson model.


1615 – 1745: “Improved Drain-Source Voltage Detection Method for Short-Circuit Protection of SiC MOSFET” Qiang Wang, Aalborg University, Denmark 

The importance of short-circuit protection in the driving scheme is self-evident, and the key is the realization of fast and accurate short-circuit fault detection. The traditional drain-source voltage (Vds) short-circuit detection method sacrifices the speed to ensure the reliability of short-circuit protection by setting a relatively large blanking time constant. However, the shorter short-circuit withstand time of SiC MOSFET puts forward a higher requirement of short-circuit protection. Therefore, the improved Vds short-circuit detection method proposed in this article enhances the self-adaptation to different short-circuit faults of SiC MOSFET, as a result speeding up the protection speed.


Thursday 25th August

0845 – 0935: Systems 1


0845 – 0910: “A PCB-Based Power Converter for e-Mobility Applications” Julien Morand, Mitsubishi Electric R&D, France

This paper presents a PCB-based packaging suitable for Silicon Carbide devices in an automotive application. The package and its assembly technique are the core of a 100 kW power converter. The converter includes a switching cell, bypass capacitors, gate driver, built-in sensors, and an output inductor. The stack-up of the PCB mixes thin and thick (up to 400 µm) copper layers providing high current carrying capabilities and superior thermal performances. In addition to the presentation of the module structure and an evaluation of the manufacturing yield, the paper shows the superior electrical switching performance and a first evaluation of the integrated sensor


0910 – 0935: “Additively Manufactured Thermally Integrated DC-DC Converter” Patrick McCluskey, University of Maryland, USA

Wide bandgap semiconductors, such as SiC, have properties that allow them to far surpass the performance of conventional silicon (Si) in power electronic applications. This makes SiC devices prime candidates for next-generation high-power switching devices for a wide range of applications. SiC power devices have demonstrated greater than twice the power density of Si power devices at greater efficiency. This paper will discuss the design of a SiC DC-DC converter with dramatic improvements in packaging density, size, and weight over current module technologies. The following three critical sections of this innovative design will be highlighted: 1) design and thermal management of the overall packaging structure; 2) thermo-mechanical reliability of the package; and 3) additive manufacturing approaches.


0935 – 1025: Diamond Semiconductors


0935 – 1000: “Diamond Power Devices: Benchmarks, Optimal Design and Integration in Power Converters” Nicolas Rouger, Université de Toulouse, France 

Wide bandgap (WBG) materials such as GaN and SiC have shown key improvements in power converters in terms of efficiency and power density. Furthermore, the next generation of power semiconductor devices based on ultra wide bandgap (UWBG) materials are currently being developed: monocrystalline diamond offers outstanding physical properties and continuous breakthroughs are achieved in wafer diameters, growth quality and specific device architectures, while new record diamond devices are being demonstrated within the research community. In this presentation, I will benchmark diamond power devices and their impacts on power converters. I will focus especially on the device architectures, results and approaches within the national project “LSD-MOSFET” funded by the French research agency, in a collaborative research with Néel Institute, Diamfab in Grenoble and Laplace in Toulouse. The optimal design of diamond Field Effect Transistors will be presented towards a breakdown voltage up to 2kV, and a high current capability thanks to vertical architectures. The unique behavior of an isolated electrical and optical gate will be detailed. Finally, the efforts needed to integrate such diamond power devices in power converters will be discussed.


1000 – 1025: “Thermo-Mechanical Constraints for Packaging of Diamond Components” Naüm Fusté, CNM Barcelona, Spain

In this work a Finite Element Simulation thermal and mechanical study of a power SOT-227 package with a diamond die is performed in order to assess the impact of its mechanical properties when compared to the standard silicon dies. Furthermore, the simulations are carried using silver sintering as die-attach material, and different conditions and parameters that affect its mechanical behaviour are explained and quantified in order to illustrate the variation in results and the need for reliable modelisation and material parameters identification. Mechanical behavioural data is also extracted for the sintered silver simulating a lap shear test, which is used to validate a non-linear identification method of the Anand model parameters. The results show that the inclusion of a diamond die increases significantly the amount of stress and plastic deformation in the die-attach layer, which will lead to reliability problems and shorter life cycle. In addition, when using silver sintering as die-attach, the model parameters should be extracted for each particular material, owing to the fact that the mechanical properties of the die-attach layer strongly depend on its processing conditions. Finally, the Anand model parameter identification routine was validated, obtaining minimum deviation from the original values used to simulate the pseudo-experimental data.


1025 – 1045: Coffee Break

1045 – 1200: Dielectrics/Insulation


1045 – 1110: “Electric Field Grading in HV Integrated Systems: State-of-the-Art and Future Prospects” Sombel Diaham, Université de Toulouse, France

Field grading materials (FGM) are a class of insulators that enable to spread high electric field spots occurring at triple points in high voltage electrical systems and leading to reliability issues. This presentation will briefly review the state-of-the-art of the field grading approaches applied to standard bonding-based power modules architecture with improved PDIV and breakdown voltage. On the other hand, the presentation will focus on promising tailored encapsulation composite design to control more efficiently and locally the field grading properties to further improve the working voltage’s packaging limit for the next generation of integrated power modules.


1110 – 1135: “Advanced Insulation Technology for Electrical and Electronic Equipment” Kenji Okamoto, Fuji Electric, Japan

Resin insulation technology, which has been developed for heavy electrical equipment such as switchgear, generators, and transformers (molded transformers) since the end of World War II, is now facing a new development. The application of solid insulation is required to expand for downsizing and high reliability. In addition, there are recent demands for environmental harmonization such as CO2 reduction, recycling, and VOC reduction. Furthermore, the importance of resin insulation technology is also increasing in the field of power semiconductor modules and power electronics to which they are applied, as the electric field becomes higher. To meet these needs, Fuji Electric has been conducting research and development on advanced resin insulation technology and environmental harmonization. In this article, we introduce some representative technologies such as downsizing of insulation spacer for gas insulated switchgear (GIS), insulation design technology for power electronics equipment under combined stress environment, and partial discharge location technology inside power modules.


1135 – 1200: “High Temperature Dielectric Properties of Aluminum Nitride Substrates with Different Amounts of Titanium” Daigo Okumura, Kyushu Institute of Technology, Japan

This paper presents investigation on the effects of titanium (Ti) addition on the dielectric and insulating properties of aluminum nitride (AlN) substrates in the high temperature range from room temperature to 400 °C. Experimental results show that as the amount of titanium added increases in the range of 1 ppm to 100 ppm, both the complex relative permittivity εr’ and the relative dielectric loss factor εr” decreases, so that the insulating performance is superior. The dielectric relaxation phenomenon was also discussed using the complex electrical modulus *. As a result, the activation energy Ea of the relaxation phenomenon increased from 1.21 eV to 4.70 eV with the addition of Ti to AlN. Next, the activation energy Eb was calculated in the same way using DC conductivity, and the results were similar to those of Ea. The increase in Ea and Eb with Ti addition was attributed to the suppression of charge diffusion at the interface between Ti and AlN phase.


1200 – 1300: Lunch

1300 – 1350: Keynote 3 – Chris Genthe, Rockwell (http://iwipp.org/keynotes/)

1350 – 1440: Systems 2

1350 – 1415: “Series Connected SiC MOSFETs Voltage Balancing: Two Methods with Adaptive Delays” Cedric Mathieu De Vienne, SuperGrid Institute, France

Power-electronics converters for energy transmission in Medium Voltage Direct Current (MVDC) require High-Voltage switches from 10 to 30 kV. Series-connection of SiC-MOSFETs is an effective alternative to achieve less complex High voltage converters. Nevertheless, Voltage balancing during switching transient remains the main challenge. Passive balancing solutions significantly increase the switching losses unlike active voltage balancing. This paper presents different embedded measurement techniques in an active gate-driver that adjusts switching delay in real-time. A measurement based on low-cost voltage comparators is compared to another based on 12-bit Analog-To-Digital-Converter. Both methods present advantages and the experimental results highlight the differences in performance. This analysis shows that acceptable voltage balancing can be achieved even with extremely simple measurements.

1415 – 1440: “10 kV SiC MOSFET Medium Voltage Modular Converter using Integrated Capacitor-Blocked Transistor (ICBT) Cells” Rolando Burgos, Virginia Tech, USA

Thermosonic wedge bonding has a number of advantages over room-temperature ultrasonic wire bonding. However, it is rarely used besides ball bonding and gold wedge applications due to the drawbacks and limitations of available heating technologies. Hesse recently introduced a novel thermosonic process using a laser-heated bonding tool which will alleviate most of the drawbacks. This paper presents the results of bonding tests that have used this novel process to bond aluminum and copper heavy wire to sheets of the same metal. The opportunity for fine gold wedge bonding using this novel approach will also be reviewed.

1440- 1500: Coffee Break

1500 – 1525: “Advanced WBG Module Packaging and EMI Self-containment Design” Fang Luo, SUNY, USA

This presentation covers the latest WBG module development from the presenter’s team. These presented high-power, high-voltage SiC module packages and GaN module packages including double-side-cooled modules, hybrid switch packaging, and hybrid low-inductance integrated packages for 3-level TNPC topologies. The speaker will share his understanding of the challenges in these module designs, including interconnection, EMI mitigation, and fabrication processes, and provide some of the potential solutions.


1525 – 1615: Keynote 4 – Mona Ghassemi, UT Dallas (http://iwipp.org/keynotes/)


1800 – 1900: Tour of G2Elab

1900 – 2100: Workshop Dinner @ G2Elab


Friday 26th August

0845 – 0935: Keynote 5 – Francesco Iannuzzo, Aalborg University (http://iwipp.org/keynotes/)

0935 – 1025: Thermal and Reliability 1


0935 – 1000: “On-Chip Junction Temperature Measurement using FBG Sensors” Sinisa Durovic, University of Manchester, United Kingdom

This talk will present the findings of a feasibility study exploring direct on-chip thermal sensing for a commercial IGBT module based on application of fibre optic Fibre Bragg (FBG) sensing. FBG sensing is EMI immune, utilises small and flexible optical fibres as sensors and is hence of considerable interest for condition monitoring applications in power electronic devices. This talk will cover the relevant application features and findings of a practical study exploring the application and performance of FBG technology for direct thermal sensing on an IGBT device.


1000 – 1025: “Mechanical Lifetime Testing of Wire-bonds and Solder Joints vs. Power Cycling” Golta Khatibi, TU Wien, Austria

Thick wire bonds are used in large scale in power semiconductor modules with a required fault-free and reliable performance of up to several decades under severe thermo-mechanical loading conditions. While common methods for qualification of the wire bonds are static pull or shear tests, time consuming active and passive thermal cycling of the entire modules provide infor-mation about the lifetime and long-term performance of the interconnects. Depending on the duration of each cycle, the required testing time to obtain a reliability diagram by power cycling test may take more than one year. Recently accelerated mechanical fatigue testing has been introduced as an alternative method for lifetime assessment of interconnects in a very short time. Using high-frequency dedicated mechanical testing setups allows to induce cyclic shear stresses Δx (as equivalent to ΔT), at the bonding interface and invoke lift-off failure which is the predominant failure mode during the operation of devices. In this talk, exemplary studies on the application of accelerated mechanical fatigue testing for evaluation of heavy Al and Cu wire bonds are presented. Based on the obtained lifetime curves and detailed failure analysis, the advantages and some restrictions of this method in comparison with power cycling are dis-cussed.


1025 – 1045: Coffee Break

1045 – 1200: Thermal and Reliability 2


1045 – 1110: “Recent Advances in Condition Monitoring for Power Semiconductors” Vincent Quemener, Mitsubishi Electric R&D, France

The temperature is a central parameter in the performances and the reliability of the power modules. In that purpose, we developed an on-line method to measure Tj based on the gate resistor as Temperature Sensitive Electrical Parameter (TSEP). This TSEP has several advantages such as the ability to measure Tj during the OFF state and ON state of the die with a precision/accuracy lower than ±6°C. The application of Tj measurement for Health Management will be illustrated with three examples. First, Tj monitoring technology was implemented at a low cost for over-temperature detection to protect the power module of catastrophic failure. Second, the junction temperature of a multi-gate power module was balanced, and the lifetime was increased. Finally, the control of the temperature of a die was performed by driving the die in linear mode during the OFF state to increase the lifetime of the power module by realizing thermal treatments of its interconnections and mitigating the thermal cycles. The junction temperature is also changed by the degradation of the interconnections and will be used to perform health monitoring. This offers even more opportunities to enhance the life-cycle of power electric systems through intelligent operation.


1110 – 1135: “Online In-Situ Device Monitoring for Real-time Diagnostics and Prognostics of Power and Circuit Protection Systems” Jim Gafford, University of North Carolina, USA

Expanding operating envelopes for power electronics systems enabled by advances in wide bandgap semiconductor devices and increasingly capable embedded control systems provide avenues for expansive commercially relevant power and energy conditioning systems. As scale and cost of these systems increase, the value of embedded diagnostic and prognostic controls are realized to improve reliability and resiliency as well as automated adaptability to variable operating conditions. The value proposition requires real-time monitoring of on-line systems. Sensing elements must be minimally invasive as to not exacerbate parasitic resistances and reactances which erode performance. In-situ sensing circuits are being demonstrated which provide these enhanced operational capabilities, such as sub-microsecond short circuit protection, power semiconductor device on-state resistance measurement, and capacitor ESR estimation. Techniques developed for the latter two measurements may be extended to numerous critical components to provide detailed real-time state of health estimation for critical components and system capabilities. These measurements can be employed beyond selection of binary operating thresholds to generate dynamic limits for mission critical operations. Thus, enhanced system reliability may be achieved while delivering the broadest application specific system capacity.


1135 – 1200: “A Novel Packaging with Direct Dielectric Liquid Cooling for High Voltage Power Electronics” Amin Al-Hinaai, Hochschule Kempten, Germany

This work investigates a packaging solution for high voltage semiconductors (20 kV), allowing for a dramatic reduction in size and complexity of power electronics modules. The standard packaging structures typically introduce a competition between electrical insulation (which requires thick insulating layers) and thermal performance (where thin, high thermal conductivity layers are preferred). Here, we introduce a concept which addresses this competition and is based on direct cooling using dielectric liquid. Single-chip heatsinks are designed, optimized using computational fluid dynamics (CFD), built and tested.


1200 – 1300: Lunch

1300 – 1350: Keynote 6 – Aaron Brovont, PC Krausse (http://iwipp.org/keynotes/)

1350 – 1500: EMI 1


1350 – 1415: “Auxiliary Circuit Design for 10kV SiC MOSFET Modules” Jun Wang, University of Nebraska-Lincoln, USA

The U.S. energy infrastructure will experience a transformational modernization and innovation in the next 5–10 years thanks to the recent significant federal investments. Medium-voltage (MV) high-power SiC modules are the enabling technology to develop a variety of high-density, high-efficiency, and robust power converters and circuit breakers to realize this ambition. The successful adoption of the cutting-edge MV SiC modules is built upon the resolution of a series of critical challenges, including gate driving, control and sensing, EMI, high-voltage insulation, and thermal management, in a bottom-up manner from the component level to the power-cell level and finally to the converter level. This talk presents systematic auxiliary circuit design solutions to tackle these challenges. Enhanced gate drivers and their power supplies, a bidirectional auxiliary power network, and synchronous distribution control systems have been proposed to address low-power-level concerns; a switching-cycle control approach for passive component reduction, a shielded laminated dc-bus, and a partial-discharge-free insulation design method have been developed to resolve high-power-level issues [4]. The electromagnetic interference, as a common issue involved in all the designs above, has been carefully contained and mitigated by proposed shielding and coupling minimization techniques. All the solutions have been successfully validated on converter platforms operating continuously with switching transient immunity up to 100 V/ns.


1415 – 1440: “Packaging Design for Low EMI Generation from Power Modules” Pierre-Olivier Jeannin, G2Elab, France

This paper investigates the impact of the design of a power module on its EMI generation, in the case of WBG components. Stray elements (inductances, capacitances) must be carefully reduced or designed, but that’s not all: shielding effect and integrated filtering are also investigated. It results in some design rules for packaging. Some examples of power modules design will be presented.


1440 – 1500: “Comparison of FEA Techniques for Estimation of Module Parasitics” Andy Lemmon, University of Alabama, USA

Finite element analysis (FEA) is a commonly used technique to estimate the parasitics of semiconductor packaging structures such as multi-chip power modules (MCPMs). The shift towards faster switching speeds and smaller packaging has led to increased interest in characterizing these parasitics in order to predict their impact on system behavior and device reliability. Several commercial software packages are available that can be employed in support of these goals. This paper seeks to compare and quantify the performance and accuracy of two software packages commonly used for this purpose – namely ANSYS Q3D extractor and COMSOL Multiphysics. A module-like structure with a flexible terminal configuration is used as a test article to support this analysis.


1500 – 1520: Goodbye Coffee